Many types of semiconductor devices such as microprocessors, and memories such as dynamic random access memories (DRAMs), static rams (SRAMs), and programmable read-only memories (PROMs) are formed in much the same way. Layers of oxide, nitride, and polycrystalline silicon (polysilicon or poly) are formed over a substrate such as monocrystalline silicon or gallium arsenide to form field and gate oxide, capacitor cell plates, word and digit lines, and various other structures.
One structure commonly formed during the manufacture of a semiconductor device such as a DRAM is a buried contact to a highly doped source (drain) area of the substrate such as that in FIGS. 1 and 2. FIG. 1 is a cross-section showing a semiconductor substrate 10 doped to a P- conductivity and a region of field oxide 12 overlying the substrate 10. An insulation layer 14 such as tetraethyl orthosilicate (TEOS) or other insulator surrounds a transistor gate 16, manufactured from a material such as doped polycrystalline silicon (poly). A mask 18 over the substrate 10 defines the etch area by protecting some regions while leaving other regions exposed. The P- substrate as shown has been lightly doped to form an N- active area 20 therein. To form the contact, an anisotropic (vertical) etch, for example, is performed on the FIG. 1 structure to remove the exposed material down the substrate. The mask is removed, and a layer of contact material 22, for example doped or undoped poly, is formed over the substrate 10 to make contact with the substrate in the contact region as shown in FIG. 2. An insulation layer (not shown) such as oxide or nitride and another conductive layer (not shown) can be formed over the first poly layer to form a storage cell having first and second capacitor cell plates and a buried contact according to means known in the art.
A transistor formed in this manner is known to have associated problems. For example, the charge can leak from the storage cell to the substrate through the buried contact junction which requires a frequent charge refresh to retain a correct data bit in the cell. This charge leakage problem is often associated with the electrical field across the junction, which depends on the doping profile near the junction. The cell leakage characteristic is thermal cycle sensitive, and any subsequent thermal cycle during processing can change the cell leakage characteristic.
A method of contact formation, and the structure resulting therefrom, which has fewer problems from diffusion and leakage would be desirable.